Numerous integrated circuit devices, structures and techniques of fabricating same, are known to the prior art. The following prior art patents and summaries are submitted to generally represent the state of the art.
Reference is made to U.S. Pat. No. 3,600,651 entitled "Bipolar and Field-Effect Transistor Using Polycrystalline Epitaxial Deposited Silicon" granted Aug. 17, 1971 to D. M. Duncan. The Duncan patent discloses adjacent layers of single crystalline and polycrystalline semiconductor material located upon a semiconductor.
Reference is made to U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure", grated Mar. 7, 1972 to D. L. Peltzer. The Peltzer patent discloses a thin silicon epitaxial layer, formed on a silicon substrate, and subdivided into electrically isolated pockets by a grid of oxidized regions of epitaxial silicon material which extend through the epitaxial layer to a laterally extending PN junction.
Reference is made to U.S. Pat. No. 3,873,372 entitled "Method for Producing Improved Transistor Devices" granted Mar. 25, 1975 to W. S. Johnson. The Johnson patent discloses methods for fabricating insulated-gate field-effect transistor devices wherein the problem of accurately aligning the gate electrode over the channel region is particularly addressed and solved.
Reference is made to U.S. Pat. No. 3,904,450 entitled "Method of Fabricating Injection Logic Integrated Circuits Using Oxide Isolation" granted Sept. 9, 1975 to W. J. Evans et al. The Evans et al patent discloses an integrated injection logic circuit cell structure and its fabrication. A pattern of oxide isolation regions is used to define, at least partially, the introduction of two types of impurities in such a way as to reduce the number of masking steps. Certain of these oxide regions do not penetrate through the conventional epitaxial layer, leaving a lateral buried path to serve as the base of a lateral injection transistor. A pattern of polycrystalline silicon containing impurities is used both as a diffusion source and an interconnection.
Reference is made to U.S. Pat. No. 3,919,005 entitled "Method For Fabricating Double-Diffused, Lateral Transistor" granted Nov. 11, 1975 to R. D. Schinella et al. The Schinella et al patent discloses a double diffused lateral transistor structure fabricated utilizing an etch resistant mask to provide self-aligning positioned accuracy for formation of active areas of the transistor. The lateral structure includes semiconductor material having at least one substantially flat surface and the structure includes at least one region of insulating material formed adjacent the flat surface, the top surface of the insulating material being substantially coplanar with said one surface. A collector is formed in the semiconductor material adjacent first portions of both the flat surface and the insulating material, while an emitter is formed in the semiconductor material adjacent second portions of both the flat surface and the insulating material. A base separates the collector from the emitter.
Reference is made to U.S. Pat. No. 3,947,299 entitled "Method of Manufacturing Semiconductor Devices" granted Mar. 30, 1976 to B. H. Weijland et al. The Weijland et al patent discloses a method of making a semiconductor device for application in a monolithic integrated circuit wherein a local buried insulating layer is provided at the interface of a substrate and a semiconductive layer is locally converted into an insulator which extends down to the buried insulator. The method is useful among other things, for providing isolated semiconductor islands.
Reference is made to U.S. Pat. No. 3,958,323 entitled "Three Mask Self Aligned IGFET Fabrication Process" granted May 25, 1976 to F. H. DeLaMoneda. The DeLaMoneda patent discloses a process for making a self aligned IGFET having a polycrystalline silicon gate, using three masking steps. Layers of silicon dioxide, polycrystalline silicon, and silicon nitride are respectively deposited on the surface of a silicon substrate of a first conductivity type. With the first mask, openings are made in regions of these layers above the proposed location for the source and drain. The source and drain are then deposited in the substrate through these openings. The disclosed process continues, growing a silicon dioxide layer on the lateral surfaces of the polysilicon gate, exposed by these openings. Then a silicon nitride layer is deposited on all exposed surfaces and a second mask is employed to permit the removal by etching of this nitride layer from all portions except the proposed location of devices metallization at a first region over the gate, a second region over the source and a third region over the drain of the device. The polycrystalline silicon layer is then etched and removed from the field region of the device. Polysilicon material in the gate region is protected during this etching step by the first nitride layer and the silicon dioxide layer grown over the lateral exposed surfaces of the gate. The nitride layer regions are then etched away and metallized contacts are formed to the source, drain and polycrystalline silicon gate regions by means of a third and last mask. Alternative steps are disclosed for making the gate and field oxide regions coplanar.
Reference is made to U.S. Pat. No. 3,961,999 entitled "Method For Forming Recessed Dielectric Isolation with A Minimized `Bird's Beak` Problem" granted June 8, 1976 to I. Antipov. The Antipov patent discloses a method for forming recessed silicon dioxide isolation in integrated circuits in which the "bird's beak" problems associated with conventional silicon dioxide silicon nitride composite masking structures is minimized. A conventional composite mask comprising a bottom layer of silicon dioxide and an upper layer of silicon nitride having a plurality of openings defining the regions in the silicon substrate which are to be thermally oxidized is formed on a silicon substrate. Recesses are then etched in the silicon substrate in registration with the openings in the composite mask. Then the silicon dioxide layer is, in effect, overetched to extend the openings in the silicon dioxide to greater lateral dimensions than the openings in the silicon nitride layer whereby the silicon nitride at the periphery of the openings is undercut. A layer of silicon is then deposited in the recesses covering the undercut portions of said silicon nitride layer. Then, the structure is subjected to thermal oxidation whereby the silicon in and abutting the recesses is oxidized to form regions of recessed silicon dioxide substantially coplanar with the unrecessed portions of the silicon substrate. Because of the undercutting and the deposition of silicon in the recesses, the "bird's beak" effect is minimized.
Reference is made to U.S. Pat. No. 4,011,105 entitled "Field Inversion Control for N-Channel Device Integrated Circuits" granted Mar. 8, 1977 to J. O. Paivinen et al. The Paivinen et al patent discloses improvement in the field inversion properties of integrated circuits incorporating N-channel MOS devices by using a silicon substrate whose bulk dopant concentration is low but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by non-selectively ion implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide. The invention allows the use of relatively inexpensive, low dopant concentration substrates to conveniently manufacture high performance N-channel MOS integrated circuits.
Reference is made to U.S. Pat. No. 4,048,649 entitled "Superimposed V-Groove Isolated Bipolar and VMOS Transistors" granted Sept. 13, 1977 to R. Bohn. The Bohn patent discloses a semiconductor structure having a compatible mixture of bipolar and unipolar transistors. In that structure a monocrystalline P-type silicon substrate is employed which has its 1-0-0 crystallographic planes at a face on which an n epitaxial layer was grown. The epitaxial layer is divided into electrically isolated parts by V-grooves that extend down through the epitaxial layer and have their apices terminating in the substrate. A thin silicon dioxide film coats the V-grooves and those grooves are filled with polycrystalline silicon. Where it is desired to use the polycrystalline silicon as the insulated gate of a field effect transistor, the polycrystalline silicon is electrically conductive. Bases for bipolar transistors are formed by diffusion of an appropriate impurity into selected areas of the epitaxial layer. The emitters, drains and sources are formed by diffusion of a different impurity. Each field effect transistor has its drain and source on adjacent parts of the epitaxial layer which are separated by the V-groove in which the gate is situated. The base and emitter of a bipolar transistor may be situated on one isolated part and the collector may be situated on an adjacent part separated by a V-groove having an electrically conductive polycrystalline filler.
Reference is made to U.S. Pat. No. 4,103,415 entitled "Insulated-Gate Field-Effect Transistor with Self-Aligned Contact Hole to Source or Drain" granted Aug. 1, 1978 to J. A. Hayes. The Hayes patent discloses an oxide layer interposed between the polysilicon gate and the contact hole to the source or drain of an insulated gate field-effect transistor to prevent electrical shorts between the gate and metal contact to the source or drain. The oxide dielectric layer enables the contact hole to be extremely close to the polysilicon gate without electrical shorts occurring therebetween, thereby eliminating the need for a minimum separation between the gate and contact hole.
Reference is made to United Kingdom Pat. Specification No. 1514624 (complete specification published June 14, 1978).
The following is an excerpt from the United Kingdom Pat. Specification No. 1514624:
In bipolar integrated circuits the functional elements are usually electrically insulated from one another by the use of special insulation-diffusion techniques. PA1 An integrated circuit of this type can, for example, be produced by depositing onto a p-doped semiconductor substrate an n-doped epitaxial layer at the surface of which an oxide layer is subsequently formed. Conventional photolithographic methods are then used to etch a frame-like structure of interconnected windows into this oxide layer through which a p-diffusion (p.sup.+ indicating a high doping concentration) is effected to a depth at which the diffusion front overlaps the p-doping of the substrate. In this way n-doped regions are obtained which are entirely enclosed by a p-n junction. When the p-doped substrate and the p.sup.+ doped insulating frames are connected to the most negative potential, all the isolating p-n junctions are biased in the blocking direction. Deep diffusion of this kind inevitably involves a lateral diffusion beneath the oxide mask, so that zones of the functional elements of the circuit, e.g., p-doped base zones of n-p-n transistors, formed in the isolated regions, must always be spaced at an adequate distance from the isolating p-doped zones. This safety clearance is determined by the diffusion depths, adjustment tolerances and space requirement, for example, of a transistor, and is, therefore, to a large extent dependent upon the space required for isolating purposes.
In order to avoid this disadvantage, the so-called isoplanar technique has been devised. In this technique a thin silicon nitride layer is applied to the surface of a silicon epitaxial layer and is etched to form a required structure in known manner. Residual portions of the nitride layer serve as a mask for the etching of a frame-like trench structure in the epitaxial layer to an etching depth of approximately half the total thickness of the epitaxial layer. During a subsequent oxidation step, the silicon exposed in the etched trenches is locally transformed into silicon dioxide, the regions lying beneath the residual portions of the nitride layer remaining unaltered since the nitride layer has a masking action as regards oxidation. The oxidation is continued until the boundary of the oxide formed has passed the p-n junction between the epitaxial layer and substrate. As a result, beneath the residual portions of the nitride layer, there remain islands of silicon which are isolated from the substrate by a p-n junction and have isolating oxide frames at their lateral boundaries.
The present trend in semiconductor technology is toward large scale integration of devices with very high speed and low power performance. The parameters that are essential to such high performance bipolar transistor are low parasitic capacitances as realized by (a) shallow vertical junction structure and (b) small horizontal geometry. To achieve these goals it is necessary to make the devices in the integrated circuits as small as possible.
With the advance in semiconductor processing technologies, such as in the fields of ion implantation, deep dielectric isolation, electron beam and x-ray lithographies, reactive ion etching, advanced insulator and polysilicon deposition techniques, and metal lift-off processes, fabrication of the ultrahigh performance integrated circuit devices can be achieved.
Ion-implanation provides a means for precisely controlling the total amount of impurity transferred to the wafer. The impurity depth distribution is accurately controlled by implant energy. Unlike the conventional thermal diffusion process ion implantation is not a high temperature process. Thus, by using photo-resist or metal masking, multiple impurity introduction operations can be achieved without resort to high temperatures. A final thermal drive-in diffusion is sufficient to anneal out the radiation damage caused by implanation, and obtain desired device junction depth. Consequently, integrated circuit devices can be made shallower, with greater precision of the impurity distribution using ion implantation technology.
As the semiconductor devices become shallower, it is desirable to reduce the overall junction area so as to reduce parasitic capacitance. Further reduction of device parasitic capacitance can be achieved by shrinking of device horizontal dimensions and using dielectric isolation. Dielectric isolation is a method of fabricating integrated circuits in which the device components are isolated by other than P-N junctions. A well known dielectric isolation namely "Recessed Oxide Isolation" (ROI) is a commonly used process in present day semiconductor technology. Using Si.sub.3 N.sub.4 as the oxidation barrier, the ROI technique is done by etching grooves into the semiconductor wafer adjacent those regions in which PN junctions are to be formed. The silicon exposed by the grooves is then thermally oxidized to form recessed oxide regions providing dielectric isolation. The problem associated with the ROI is the formation of "bird's head" and bird's beak" structure at the lateral edges of recessed oxide. The bird's head is undesirable because it can cause breaks or discontinuities in thin films covering the steps. The indefiniteness of bird's beak structure reduces the available active surface area and, therefore, imposes the need for wider tolerance of lateral dimension in the integrated circuit layout. A newly developed oxide isolation called "Deep Dielectric Isolation" (DDI) avoids the above mentioned ROI problem. The DDI process utilizes reactive-ion etching (RIE) to form deep narrow trenches into the wafer surrounding those regions in which devices are to be formed. [Reference is made to U.S. Pat. No. 4,104,086, entitled "Method For Forming Isolated Regions of Silicon Utilizing Reactive Ion Etching" granted Aug. 1, 1978 to J. A. Bondur et al., and U.S. Pat. No. 4,139,442 entitled "Reactive Ion Etching Method For Producing Deep Dielectric Isolation in Silicon" granted Feb. 13, 1979 to J. A. Bondur et al., respectively assigned to the assignee of the subject application]. The trenches are overfilled with SiO.sub.2 put down by chemical vapor deposition (CVD) technique. The overfilled SiO.sub.2 also planarizes the device surface. A blanket RIE back-etching to the semiconductor surface yields deep oxide isolation trenches. Unlike the bird's beak in ROI structure, sidewall of the DDI structure is nearly vertical. The surface of DDI regions and the silicon where devices are to be formed are coplanar. With the DDI, doping process for various device regions is then self-aligned by oxide isolation. The self-aligned process eliminates precise mask alignment steps and also saves a number of mask steps in the device fabrication.
As mentioned above the DDI enables us to form devices with considerably smaller cell size than those formed by using either P-N isolation or by ROI. Further reduction of device horizontal dimensions requires the use of high resolution capabilities of lithography and etching processes. The electron beam lithography is the most promising method for delineating submicron size device patterns. For device window opening the reactive ion etching (RIE) is the most attractive alternative of the conventional wet solution etching. The RIE is a dry process having directional etching characteristic. The etched device windows preserve the lithography defined etch mask dimensions, and the openings have vertical sidewalls. Thus, the E-beam lithography and reactive ion etching are compatible for fabricating very small device geometries.
For the very small bipolar transistor devices, as for example, micron size transistors, the base areas and, therefore, the collector-base parasitic capacitance is the most significant performance parameter. In the bipolar transistor the active base area is the region below the emitter. In the conventional transistors, fabricated by the prior art, the base contacts are formed above the inactive base area surrounding the emitter. The transistor base area that is needed to accommodate the emitter and base contacts is considerably larger than the active base area. To reduce the base area for making ultrahigh performance bipolar transistors, a different approach in making base contact is desirable.